Performing Autonomous Path Navigation Using Deep Neural Networks

Figure 1 illustrates a flowchart of a method for performing autonomous path navigation using deep neural networks 100 for performing autonomous path navigation using deep neural networks, in accordance with one embodiment. As shown in operation 102, image data is received at a deep neural network (DNN) 102. In one embodiment, the image data may include a pictorial image. In another embodiment, the image data may include a plurality of pictorial images. In yet another embodiment, the image data may be derived from video data (e.g., streaming video, etc.). 

Additionally, in one embodiment, the image data may includeoptical data, infrared data, light detection and ranging (LIDAR) data, radar data, depth data, sonar data, etc. In another embodiment, the image data may includestereo image data received from a plurality of imaging devices. In yet another embodiment, the image data may be received from one or more imaging devices. For example, the image data may be received from a digital imaging camera, a radar device, a LIDAR device, an infrared imaging device, a sonar imaging device, etc. 

Further, in one embodiment, the image data may be received in real-time from the one or more imaging devices. In another embodiment, the image data may be received from one or more hardwareimaging devices, utilizing middleware (e.g., a ROS, etc.). In yet another embodiment, the image data may be received at a vehicle that includes the one or more imaging devices. For example, the vehicle may include any controlled mobile object, such as an automobile, airplane, amphibious vehicle (e.g., a boat, hydroplane, etc.) drone, micro aerial vehicle (MAV), rover, etc. In another example, the middleware may be running on hardware installed within the vehicle. In yet another example, the one or more cameras may be installed within the vehicle. 

Further still, in one embodiment, the image data may indicate a current location of the vehicle on a path. For example, the one or more imaging devices may be mounted on the vehicle such that the image data created by the one or more imaging devices indicates the current location of the vehicle on the path. In another embodiment, the DNN may include a supervised classification network. 

For example, the image data may includesupervised data that is correctly labeled with an associated position. In another example, the DNN may be trained with image data having associated correct labels. In another embodiment, the DNN may implement a loss function. For example, the DNN may determine a label for the image data, compare the label to the associated correct label for the image data, and may compute a difference between the labels. In another example, the DNN may be adjusted, based on the difference between the labels, using back propagation. 

In this way, the DNN may be more likely to correctly label image data during subsequent iterations. 

Also, as shown in operation 104, the DNN determines both an orientation of a vehicle with respect to a path and a lateral position of the vehicle with respect to the path, utilizing the image data 104. In one embodiment, the path may include any course that may be identified visually within the image data. In another embodiment, the path may include a trail, one or more tracks (e.g., train tracks, tire tracks, etc.), one or more power lines, a street, a culvert (e.g., a sewer culvert, etc.), an urban canyon, etc. 

In addition, in one embodiment, the vehicle may include the vehicle running middleware and the one or more imaging devices. In another embodiment, the vehicle may currently be in motion (e.g., along the path, etc.). In yet another embodiment, the orientation with respect to the path may include a plurality of probabilities. For example, the orientation with respect to the path may include a probability that a vehicle is currently facing left with respect to the path, a probability that a vehicle is currently facing right with respect to the path, and a probability that a vehicle is currently facing straight with respect to the path. In another example, each of the plurality of possibilities may be represented numerically, resulting in three numbers output by the DNN that indicate the orientation with respect to the path. 

Furthermore, in one embodiment, the lateral position with respect to the path may include a plurality of probabilities. In another embodiment, the lateral position with respect to the path may identify a probability of a plurality of lateral offsets with respect to the pathcenter. For example, the lateral position with respect to the path may include a probability that a vehicle is currently shifted left with respect to the path, a probability that a vehicle is currently shifted right with respect to the path, and a probability that a vehicle is centered with respect to the path. In another example, each of the plurality of possibilities may be represented numerically, resulting in three numbers output by the DNN that indicate the lateral position with respect to the path. 

Further still, in one embodiment, the orientation and lateral position may be determined in real-time within the vehicle. In another embodiment, the image data may be sent from the vehicle to a remote location (e.g., a distributed computing environment), and the orientation and lateral position may be determined at the remote location. 

In this way, both rotation and translation data may be determined by the DNN, utilizing the image data. 

Also, as shown in operation 106, a location of the vehicle is controlled, utilizing the orientation of the vehicle with respect to the path and the lateral position of the vehicle with respect to the path 106. In one embodiment, the orientation of the vehicle with respect to the path and the lateral position of the vehicle with respect to the path may be converted into steering directions. For example, the conversion may be performed by a controller module. In another example, the steering directions may include one or more steering signals (e.g., a steering angle, etc.). 

Additionally, in one embodiment, the steering directions may be converted into another protocol to create convertedsteering directions. For example, the steering directions may be converted from a middlewareprotocol (e.g., a ROS protocol, etc.) to a vehicle control protocol. In another example, the conversion may be performed by a communication module. 

Furthermore, in one embodiment, the convertedsteering directions may be sent to a vehicle systems module to control one or more steering mechanisms of the vehicle. For example, the one or more steering mechanisms of the vehicle may control a direction in which the vehicle is moving. In another example, the convertedsteering directions may be sent to the vehicle systems module utilizing a communication protocol. 

Further still, in one embodiment, the one or more steering mechanisms may be adjusted, based on the convertedsteering directions. For example, the one or more steering mechanisms may be adjusted by the vehicle systems module to move the vehicle laterally to the center of the path. In another example, the one or more steering mechanisms may be adjusted to move the vehicle so that the orientation of the vehicle is straight with respect to the path. In another embodiment, the vehiclelocation controlling may be performed in real-time within the vehicle. 

Also, in one embodiment, the DNN may control directional stability by utilizing predictions with a reduced confidence. For example, the DNN may implement a classification scheme with a reduced confidence for more smooth and stable vehicledirection control. 

In addition, in one embodiment, a second DNN may perform object detection within the path. For example, the second DNN may be included within the vehicle and may communicate to other modules within the vehicles (e.g., via middleware, etc.). In another example, the second DNN may receive the image data, and may outputobject data indicating whether an object (e.g., a person, animal, etc.) is in the image data. In yet another example, the object data may be sent from the second DNN to the controller module (e.g., via middleware, etc.). In still another example, the controller module may determine whether a size of the object in the image data is a predetermined percentage of a size of the image in the image data. 

Further, in one example, the controller module may send one or more commands to the vehiclesystems (e.g., to change a course of the vehicle, to stop a functioning of the vehicle, etc.) in response to determining that the size of the object in the image data is equal to or greater than the predetermined percentage of the size of the image in the image data. This may provide a safety mechanism that may stop the vehicle when an object of a predetermined size is on the path. 

Further still, in one embodiment, a third DNN may perform obstacle detection associated with the path. For example, the third DNN may be included within the vehicle and may communicate to other modules within the vehicles (e.g., via middleware, etc.). In another example, the third DNN may receive the image data, and may outputobstacle data such as a set of weights indicating a likelihood of one or more obstacles at various locations and distances along the path. For instance, the third DNN may implement simultaneous localization and mapping (SLAM) to identify a location of the vehicle within a scene indicated by the image data and provide information about a relative location of static objects within the scene. 

Also, in one example, the obstacle data may be sent from the third DNN to the controller module (e.g., via middleware, etc.). In another example, the controller module may adjust the location of the vehicle, utilizing the obstacle data. This may help the vehicle avoid static obstacles in an alongside the path. 

In this way, a vehicle may be autonomously controlled, utilizing steering directions derived from DNN analysis of image data. Additionally, a DNN may perform an estimation of both vehicleorientation (3 classes) and lateral position with respect to path (3 more classes), for a total of 6 classes. Further, a loss function may be implemented during specific DNN training. Further still, a reduced confidenceimplementation may be performed within a DNN. Also, object and obstacle detection may be performed during autonomous navigation via additional DNNs. In addition, these features may be implemented utilizing on-board, real-time processing.

Figure 2 illustrates a parallelprocessing unit PPU 202, in accordance with one embodiment. In one embodiment, the PPU 202 is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU 202 is a latency hiding architecture designed to processmany threads in parallel. A thread (i.e., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU 202. In one embodiment, the PPU 202 is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display devices such as a liquid crystal display (LCD) device. In other embodiments, the PPU 202 may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same 

One or more PPU 202 s may be configured to accelerate thousands of High Performance Computing (HPC), data center, and machine learning applications. The PPU 202 may be configured to accelerate numerous deep learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like. 

As shown in Figure 2, the PPU 202 includes an Input/Output I/O unit 208, a front end unit 212, a scheduler units 214, a work distribution unit 216, a hub 210, a crossbarXBar 218, one or more general processing clusters GPCs 204, and one or more memory partition unit 220 s. The PPU 202 may be connected to a host processor or other PPU 202 s via one or more high-speed NVLinkNVLinks 206 interconnect. The PPU 202 may be connected to a host processor or other peripheral devices via an interconnect 224. The PPU 202 may also be connected to a local memory comprising a number of memory devicess 222 s. In one embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices. The DRAM devices may be configured as a high-bandwidth memory (HBM) subsystem, with multiple DRAM dies stacked within each device. 

The NVLinks 206  interconnect enables systems to scale and include one or more PPU 202 s combined with one or more CPU, supports cache coherence between the PPU 202  and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLinks 206 through the hub 210 to/from other units of the PPU 202 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLinks 206 is described in more detail in conjunction with Figure 5.

The I/O unit 208 is configured to transmit and receive communications (i.e., commands, data, etc.) from a host processor (not shown) over the interconnect 224. The I/O unit 208 may communicate with the host processor directly via the interconnect 224 or through one or more intermediate devices such as a memory bridge. In one embodiment, the I/O unit 208 may communicate with one or more other processors, such as one or more the PPU 202 s via the interconnect 224. In one embodiment, the I/O unit 208 implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect 224 is a PCIe bus. In alternative embodiments, the I/O unit 208 may implement other types of well-known interfaces for communicating with external devices. 

The I/O unit 208 decodes packets received via the interconnect 224. In one embodiment, the packets represent commands configured to cause the PPU 202 to perform various operations. The I/O unit 208 transmits the decoded commands to various other units of the PPU 202 as the commands may specify. For example, some commands may be transmitted to the front end unit 212. Other commands may be transmitted to the hub 210 or other units of the PPU 202 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit 208 is configured to route communications between and among the various logical units of the PPU 202. 

In one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU 202 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (i.e., read/write) by both the host processor and the PPU 202. For example, the host interface unit 202 may be configured to access the buffer in a system memory connected to the interconnect 224 via memory requests transmitted over the interconnect 224 by the I/O unit 208. In one embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 202. The front end unit 212 receives pointers to one or more command streams. The front end unit 212 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU 202. 

The front end unit 212 is coupled to a scheduler units 214 that configures the various GPCs 204 to process tasks defined by the one or more streams. The scheduler units 214 is configured to track state information related to the various tasks managed by the scheduler units 214. The state may indicate which GPCs 204 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler units 214 manages the execution of a plurality of tasks on the one or more GPCs 204. 

The scheduler units 214 is coupled to a work distribution unit 216 that is configured to dispatch tasks for execution on the GPCs 204. The work distribution unit 216 may track a number of scheduled tasks received from the scheduler units 214. In one embodiment, the work distribution unit 216 manages a pending task pool and an active task pool for each of the GPCs 204. The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPCs 204. The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the GPCs 204. As a GPCs 204 finishes the execution of a task, that task is evicted from the active task pool for the GPCs 204 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPCs 204. If an active task has been idle on the GPCs 204, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPCs 204 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPCs 204. 

The work distribution unit 216 communicates with the one or more GPCs 204 via XBar 218. The XBar 218 is an interconnect network that couples many of the units of the PPU 202 to other units of the PPU 202. For example, the XBar 218 may be configured to couple the work distribution unit 216 to a particular GPCGPC 204. Although not shown explicitly, one or more other units of the PPU 202 may also be connected to the XBar 218 via the hub 210. 

The tasks are managed by the scheduler units 214 and dispatched to a GPCs 204 by the work distribution unit 216. The GPCs 204 is configured to process the task and generate results. The results may be consumed by other tasks within the GPCs 204, routed to a different GPCs 204 via the XBar 218, or stored in the memory devicess 222. The results can be written to the memory devicess 222 via the memory partition unit 220, which implement a memory interface for reading and writing data to/from the memory devicess 222. The results can be transmitted to another memory devicess 222 or CPU via the NVLinks 206. In one embodiment, the PPU 202 includes a number U of memory partition unit 220 that is equal to the number of separate and distinct memory devicesmemory devicess 222 coupled to the PPU 202. A memory partition unit 220 will be described in more detail below in conjunction with Figure 4. 

In one embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 202. In one embodiment, multiple compute applications are simultaneously executed by the PPU 202 and the PPU 202 provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (i.e., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 202. The driver kernel outputs tasks to one or more streams being processed by the PPU 202. Each task may comprise one or more groups of related threads, referred to herein as a warp. In one embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. Threads and cooperating threads are described in more detail in conjunction with Figure 5. 

Figure 3 illustrates a GPCs 204 of the PPU 202 of Figure 2, in accordance with one embodiment. As shown in Figure 3, each GPCs 204 includes a number of hardware units for processing tasks. In one embodiment, each GPCs 204 includes a pipeline manager 302, a pre-raster operations, PROP unit 310, a raster engine 312, a work distributioncrossbarWDX 318, a memory management unitMMU 314, and one or more dataprocessing Clusters DPCs 318. It will be appreciated that the GPCs 204 of Figure 3 may includeother hardware units in lieu of or in addition to the units shown in Figure 3. 

In one embodiment, the operation of the GPCs 204 is controlled by the pipeline manager 302. The pipeline manager 302 manages the configuration of the one or more DPCs 318 for processing tasks allocated to the GPCs 204. In one embodiment, the pipeline manager 302 may configure at least one of the one or more DPCs 318 to implement at least a portion of a graphics rendering pipeline. For example, DPCs 318 may be configured to execute a vertex shader program on the programmable streaming multiprocessor SM 306. The pipeline manager 302 may also be configured to route packets received from the work distribution unit 216 to the appropriate logical units within the GPCs 204. For example, some packets may be routed to fixed function hardware units in the PROP unit 310 and/or raster engine 312 while other packets may be routed to the DPCs 318 for processing by the primitive engine 304 or the SM 306. In one embodiment, the pipeline manager 302 may configure at least one of the one or more DPCs 318 to implement a neural network model and/or a computing pipeline. 

The PROP unit 310 is configured to route data generated by the raster engine 312 and the DPCs 318 to a Raster Operations (ROP) unit in the memory partition unit 220, described in more detail in conjunction with Figure 4. The PROP unit 310 may also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and the like. 

The raster engine 312 includes a number of fixed function hardware units configured to perform various raster operations. In one embodiment, the raster engine 312 includes a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, and a tile coalescing engine. The setup engine receives transformed vertices and generates plane equations associated with the geometric primitive defined by the vertices. The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine is transmitted to the culling engine where fragments associated with the primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. Those fragments that survive clipping and culling may be passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. The output of the raster engine 312comprisesfragments to be processed, for example, by a fragment shader implemented within DPCs 318. 

Each DPCs 318 included in the GPCs 204 includes an M-Pipe Controller MPC 308, a primitive engine 304, and one or more SM 306 s. The MPC 308 controls the operation of DPCs 318, routing packets received from the pipeline manager 302 to the appropriate units in the DPCs 318. For example, packets associated with a vertex may be routed to the primitive engine 304, which is configured to fetch vertex attributes associated with the vertex from the memory devicess 222. In contrast, packets associated with a shader program may be transmitted to the SM 306.

The SM 306comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each SM 306 is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In one embodiment, the SM 306 implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (i.e., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the SM 306 implements a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In one embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency. The SM 306 will be described in more detail below in conjunction with Figure 5. 

The MMU 314 provides an interface between the GPCs 204 and the memory partition unit 220. The MMU 314 may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In one embodiment, the MMU 314 provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory devicess 222.

 Figure 4 illustrates a memory partition unit 220 of the PPU 202 of Figure 2, in accordance with one embodiment. As shown in Figure 4, the memory partition unit 220 includes a Raster Operations (ROP) unit 402, a level two (L2) cache 404, and a memory interface 406. The memory interface 406 is coupled to the memory 220. Memory interface 406 may implement 32, 64, 128, 1024-bit data buses, or the like, for high-speed data transfer. In one embodiment, the PPU 202 incorporates u memory interface 406 s, one memory interface 406 per pair of memory partition unit 220 s, where each pair of memory partition unit 220 s is connected to a corresponding memory devices 222. For example, PPU 202 may be connected to up to y memory devicesmemory devicess 222 s, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory (GDDR5 SDRAM). 

In one embodiment, the memory interface 406 implements an HBM2 memory interface and y equalshalf U. In one embodiment, the HBM2 memory stacks are located on the same physical package as the PPU 202, providingsubstantial power and area savings compared with conventional GDDR5 SDRAMSDRAM systems. In one embodiment, each HBM2 stack includes four memory dies and y equals 4, with HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. 

In one embodiment, the memory partition unit 220 supports Single-Error Correcting Double-Error Detecting (SECDED) Error Correction Code (ECC) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where PPU 202 s processvery large datasets and/or run applications for extended periods. 

In one embodiment, the PPU 202 implements a multi-level memory hierarchy. In one embodiment, the memory partition unit 220 supports a unified memory to provide a single unified virtual address space for CPU and PPU 202 memory, enabling data sharing between virtual memory systems. In one embodiment the frequency of accesses by a PPU 202 to memory located on other processors is traced to ensure that memory pages are moved to the physical memory of the PPU 202 that is accessing the pages more frequently. In one embodiment, the NVLinks 206 supports address translation services allowing the PPU 202 to directly access a CPU‘s page tables and providingfull access to CPUmemory by the PPU 202. 

In one embodiment, copy enginestransferdata between multiple PPU 202 s or between PPU 202 s and CPUs. The copy engines can generate page faults for addresses that are not mapped into the page tables. The memory partition unit 220 can then service the page faults, mapping the addresses into the page table, after which the copy engine can perform the transfer. In a conventional system, memory is pinned (i.e., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. With hardware page faulting, addresses can be passed to the copy engines without worrying if the memory pages are resident, and the copy process is transparent. 

Data from the memory partition unit 220 or other system memory may be fetched by the memory partition unit 220 and stored in the l2 cache 404, which is located on-chip and is shared between the various GPCs 204 s. As shown, each memory partition unit 220 includes a portion of the l2 cache 404 associated with a corresponding memory devicess 222. Lower level caches may then be implemented in various units within the GPCs 204 s. For example, each of the SM 306 s may implement a level one (L1) cache. The l1 cache is private memory that is dedicated to a particular SM 306. Data from the l2 cache 404 may be fetched and stored in each of the l1 caches for processing in the functional units of the SM 306 s. The l2 cache 404 is coupled to the memory interface 406 and the XBar 218. 

The ROP unit 402 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. The ROP unit 402 also implements depth testing in conjunction with the raster engine 312, receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine 312. The depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the ROP unit 402 updates the depth buffer and transmits a result of the depth test to the raster engine 312. It will be appreciated that the number of memory partition unit 220 s may be different than the number of GPCs 204 s and, therefore, each ROP unit 402 may be coupled to each of the GPCs 204 s. The ROP unit 402 tracks packets received from the different GPCs 204 s and determines which GPCs 204 that a result generated by the ROP unit 402 is routed to through the XBar 218. 

Figure 5 illustrates the streaming multi-processor 306 of Figure 3, in accordance with one embodiment. As shown in Figure 5, the SM 306 includes an instruction cache 502, one or more scheduler units 214 s, a register file 506, one or more processing cores 508 s, one or more special function unitsSFUs 604, one or more load/store unitsLSUs 512, an interconnect network 514, a shared memory/L1 cache 516. 

As described above, the work distribution unit 216 dispatches tasks for execution on the GPCs 204 s of the PPU 202. The tasks are allocated to particular DPCs 318 within a GPCs 204 and, if the task is associated with a shader program, the task may be allocated to an SM 306. The scheduler units 214 receives the tasks from the work distribution unit 216 and manages instruction scheduling for one or more thread blocks assigned to the SM 306. The scheduler units 214schedulesthread blocks for execution as warps of parallel threads, where each thread block is allocated at least one warp. In one embodiment, each warp executes32 threads. The scheduler units 214 may manage a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (i.e., processing cores 508 s, SFUs 604, and LSUs 512) during each clock cycle. 

Cooperative groups is a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, enabling the expression of richer, more efficient parallel decompositions. Cooperative launch APIs support synchronization amongst thread blocks for the execution of parallel algorithms. Conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (i.e., the syncthreads( ) function). However, programmers would often like to define groups of threads at smaller than thread block granularities and synchronize within the defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. 

Cooperative groups enables programmers to define groups of threads explicitly at sub-block (i.e., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on the threads in a cooperative group. The programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. Cooperative Groups primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks. 

A dispatch unit 504 is configured to transmit instructions to one or more of the functional units. In the embodiment, the scheduler units 214 includes two dispatch unit 504 s that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler units 214 may include a single dispatch unit 504 or additional dispatch unit 504 s. 

Each SM 306 includes a register file 506 that provides a set of registers for the functional units of the SM 306. In one embodiment, the register file 506 is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 506. In another embodiment, the register file 506 is divided between the different warps being executed by the SM 306. The register file 506 provides temporary storage for operands connected to the data paths of the functional units. 

Each SM 306comprises L processing cores 508 s. In one embodiment, the SM 306 includes a large number (e.g., 128, etc.) of distinct processing cores 508 s. Each processing cores 508 may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmeticlogic unit and an integer arithmetic logic unit. In one embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In one embodiment, the processing cores 508 s include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores. 

Tensor cores configured to perform matrix operations, and, in one embodiment, one or more tensor cores are included in the processing cores 508 s. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In one embodiment, each tensor core operates on a 4.times.4 matrix and performs a matrix multiply and accumulateaccumulate operation D=A.times.B+C, where A, B, C, and D are 4.times.4 matrices. 

In one embodiment, the matrix multiplyinputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point matrices. Tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4.times.4.times.4 matrix multiply. In practice, tensor cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16.times.16 size matrices spanning all 32 threads of the warp. 

Each SM 306 also comprises M SFUs 604 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In one embodiment, the SFUs 604 may include a tree traversal unit configured to traverse a hierarchical tree data structure. In one embodiment, the SFUs 604 may includetexture unit configured to perform texture map filtering operations. In one embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory 220 and sample the texture maps to produce sampled texture values for use in shader programs executed by the SM 306. In one embodiment, the texture maps are stored in the shared memory/L1 cache 516. The texture unitsimplement texture operations such as filtering operations using mip-maps (i.e., texture maps of varying levels of detail). In one embodiment, each SM 340 includes two texture units. 

Each SM 306 also comprises N LSUs 512 that implement load and store operations between the shared memory/L1 cache 516 and the register file 506. Each SM 306 includes an interconnect network 514 that connects each of the functional units to the register file 506 and the LSUs 512 to the register file 506, shared memory/L1 cache 516. In one embodiment, the interconnect network 514 is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file 506 and connect the LSUs 512 to the register file and memory locations in shared memory/L1 cache 516. 

The shared memory/L1 cache 516 is an array of on-chip memory that allows for data storage and communication between the SM 306 and the 304 435 and between threads in the SM 306. In one embodiment, the shared memory/L1 cache 516comprises 128 KB of storage capacity and is in the path from the SM 306 to the memory partition unit 220. The shared memory/L1 cache 516 can be used to cachereads and writes. One or more of the shared memory/L1 cache 516, l2 cache 404, and memory 220 are backing stores. 

Combining data cache and shared memory functionality into a single memoryblock provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache 516 enables the shared memory/L1 cache 516 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data. 

When configured for general purposeparallelcomputation, a simpler configuration can be used compared with graphics processing. Specifically, the fixed function graphics processing units shown in Figure 2, are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit 216 assigns and distributes blocks of threads directly to the DPCs 318. The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the SM 306 to execute the program and perform calculations, shared memory/L1 cache 516 to communicate between threads, and the LSUs 512 to read and write global memory through the shared memory/L1 cache 516 and the memory partition unit 220. When configured for general purposeparallelcomputation, the SM 306 can also write commands that the scheduler units 214 can use to launch new work on the DPCs 318. 

The PPU 202 may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In one embodiment, the PPU 202 is embodied on a single semiconductor substrate. In another embodiment, the PPU 202 is included in a system-on-a-chip (SoC) along with one or more other devices such as additional PPU 202 s, the memory 204, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like. 

In one embodiment, the PPU 202 may be included on a graphics card that includes one or more memory devicess 222 s. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU 202 may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard. 

Exemplary Computing System

systems with multiple GPUs and CPUs are used in a variety of industries as developers expose and leverage more parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to many thousands of compute nodes are deployed in data centers, research facilities, and supercomputers to solve ever larger problems. As the number of processing devices within the high-performance systems increases, the communication and data transfer mechanisms need to scale to support the increased 

Figure 6 is a conceptual diagram of a processing system 600 implemented using the PPU 202 of Figure 2, in accordance with one embodiment. The exemplary system 700 may be configured to implement the method 100 shown in FIG. 1. The processing system 600 includes a CPU 602, switch 604, and multiple PPU 202 s each and respective memories 220. The NVLinks 206 provides a high-speed communication links between each of the PPU 202 s. The switch 604interfaces between the interconnect 224 and the CPU 602. The PPU 202 s, memories 220, and NVLinks 206 s may be situated on a single semiconductor platform to form a parallel processing module 606. 

In the context of the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit fabricated on a die or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation and make substantial improvements over utilizing a conventional bus implementation. Of course, the various circuits or devices may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. Alternately, the parallel processing module 606 may be implemented as a circuit board substrate and each of the PPU 202 s and/or memories 220 may be packaged devices. In one embodiment, the CPU 602, switch 604, and the parallel processing module 606 are situated on a single semiconductor platform. 

In one embodiment, the signaling rate of each NVLinks 206 is 20 to 25 Gigabits/second and each PPU 202 includes six NVLinks 206interfaces (as shown in Figure 6, five NVLinks 206interfaces are included for each PPU 202). Each NVLinks 206 provides a data transfer rate of 25 Gigabytes/second in each direction, with six linksproviding 200 Gigabytes/second. The NVLinks 206 s can be used exclusively for PPU-to-PPU communication as shown in Figure 6, or some combination of PPU-to-PPU and PPU-to-CPU, when the CPU 602 also includes one or more NVLink 206 interfaces. 

In one embodiment, the NVLinks 206 allows direct load/store/atomic access from the CPU 602 to each PPU‘s 200 memory 220. In one embodiment, the NVLinks 206 supports coherency operations, allowing data read from the memories 220 to be stored in the cache hierarchy of the CPU 602, reducing cache access latency for the CPU 602. In one embodiment, the NVLinks 206 includes support for address translation services (ATS), allowing the PPU 202 to directly access page tables within the CPU 602. One or more of the NVLinks 206 s may also be configured to operate in a low-power mode. 

Figure 7 illustrates an exemplary system 700 in which the various architecture and/or functionality of the various previous embodiments may be implemented. The exemplary system 700 may be configured to implement the method for performing autonomous path navigation using deep neural networks 100 shown in Figure 1. 

As shown, an exemplary system 700 is provided including at least one central processing unit 602 that is connected to a communication bus712 (deleted). The communication bus712 (deleted) may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The exemplary system 700 also includes a main memory 702. Control logic (software) and data are stored in the main memory 702 which may take the form of random access memory (RAM). 

The exemplary system 700 also includes input devices 708, the parallel processing system 606, and display devices 706, i.e. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices 708, e.g., keyboard, mouse, touchpad, microphone, and the like. Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the exemplary system 700. Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. 

Further, the exemplary system 700 may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the internet, peer-to-peer network, cable network, or the like) through a network interface 704 for communication purposes. 

The exemplary system 700 may also include a secondary storage (not shown). The secondary storage608 (deleted) includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash memory. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner. 

Computer programs, or computer control logic algorithms, may be stored in the main memory 702 and/or the secondary storage. Such computer programs, when executed, enable the exemplary system 700 to perform various functions. The main memory 702, the storage, and/or any other storage are possible examples of computer-readable media. 

The architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the exemplary system 700 may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic. 

While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. 

Machine Learning

deep neural networks (DNNs) developed on processors, such as the PPU 202 have been used for diverse use cases, from self-driving cars to faster drug development, from automatic image captioning in online image databases to smart real-time language translation in video chat applications. Deep learning is a technique that models the neural learning process of the human brain, continually learning, continually getting smarter, and delivering more accurate results more quickly over time. A child is initially taught by an adult to correctly identify and classify various shapes, eventually being able to identify shapes without any coaching. Similarly, a deep learning or neural learning system needs to be trained in object recognition and classification for it get smarter and more efficient at identifying basic objects, occluded objects, etc., while also assigning context to objects. 

At the simplest level, neurons in the human brain look at various inputs that are received, importance levels are assigned to each of these inputs, and output is passed on to other neurons to act upon. An artificial neuron or perceptron is the most basic model of a neural network. In one example, a perceptron may receive one or more inputs that represent various features of an object that the perceptron is being trained to recognize and classify, and each of these features is assigned a certain weight based on the importance of that feature in defining the shape of an object. 

A deep neural network (DNN) model includes multiple layers of many connected perceptrons (e.g., nodes) that can be trained with enormous amounts of input data to quickly solve complex problems with high accuracy. In one example, a first layer of the DLL model breaks down an input image of an automobile into various sections and looks for basic patterns such as lines and angles. The second layer assembles the lines to look for higher level patterns such as wheels, windshields, and mirrors. The next layer identifies the type of vehicle, and the final few layers generate a label for the input image, identifying the model of a specific automobile brand. 

Once the DNN is trained, the DNN can be deployed and used to identify and classify objects or patterns in a process known as inference. Examples of inference (the process through which a DNN extracts useful information from a given input) include identifying handwritten numbers on checks deposited into ATM machines, identifying images of friends in photos, delivering movie recommendations to over fifty million users, identifying and classifying different types of automobiles, pedestrians, and road hazards in driverless cars, or translating human speech in real-time. 

During training, data flows through the DNN in a forward propagation phase until a prediction is produced that indicates a label corresponding to the input. If the neural network does not correctly label the input, then errors between the correct label and the predicted label are analyzed, and the weights are adjusted for each feature during a backward propagation phase until the DNN correctly labels the input and other inputs in a training dataset. Training complex neural networks requires massive amounts of parallel computing performance, including floating-point multiplications and additions that are supported by the PPU 202. Inferencing is less compute-intensive than training, being a latency-sensitive process where a trained neural network is applied to new inputs it has not seen before to classify images, translate speech, and generally infer new information. 

Neural networks rely heavily on matrix math operations, and complex multi-layered networks require tremendous amounts of floating-point performance and bandwidth for both efficiency and speed. With thousands of processing cores, optimized for matrix math operations, and delivering tens to hundreds of TFLOPS of performance, the PPU 202 is a computing platform capable of delivering performance required for deep neural network-based artificial intelligence and machine learning applications. 

Figure 8 illustrates an exemplary system 700 for performing autonomous path navigation using deep neural networks, according to one embodiment. As shown, the exemplary system 700 includes a camera module 804 in communication with a TrailNet DNN module 806, an object detection DNN module 808, and an obstacle detector module 810. In one embodiment, the camera module 804 may provide visualization data (e.g., image data, radar data, depth data, lidar data, infrared data, sonar data, etc.) to the TrailNet DNN module 806, the object detection DNN module 808, and the obstacle detector module 810. In another embodiment, the camera module may manage one or more cameras of a variety of different types within a vehicle. 

Additionally, in one embodiment, the TrailNet DNN module 806 may receive visualization data from the camera module 804, and may outputvehicle location information. For example, the TrailNet DNN module 806 may outputthree numbers that indicate the orientation of the vehicle with respect to the path, and three numbers output by the DNN that indicate the lateral position of the vehicle with respect to the path. 

Further, in one embodiment, the object detection DNN module 808 may receive visualization data from the camera module 804, and may output an indication as to whether a person or large animal is present within the visualization data (e.g., utilizing a DNN such as a YOLO DNN, etc.). In another embodiment, the obstacle detector module 810 may receive visualization data from the camera module 804, and may output a set of weights indicating a likelihood of obstacles at various locations and distances (e.g., utilizing simultaneous location and mapping (SLAM), etc.). In this way, the obstacle detector module 810 may identify a location of a camera within a scene, and may provide information about a relative location of static objects within the scene. 

Further still, the exemplary system 700 includes a controller module 812. In one embodiment, the controller module 812 may receive vehicle location information from the TrailNet DNN module 806 (e.g., representing the vehicle’spath orientation and lateral position), and may create steering directions (e.g., a steering angle for the vehicle, etc.), utilizing the vehicle location information. 

Also, the exemplary system 700 includes a communication module 814. The communication module 814 may receive the steering directions in a first format (e.g., a ROS protocol, etc.) from the controller module 812, and may convert then to messages in a second format (e.g., an MAV protocol, etc.). The communication module 814 may then broadcast the converted messages in the second format to a vehicle systems module 818, utilizing a communication protocol 816. 

In addition, in one embodiment, the vehicle systems module 818 may receive the converted messages, and may use such messages to control one or more physical components of the vehicle (e.g., in order to control movement of the vehicle, etc.). In this way, the controller module 812 may compute steering directions and send the steering directions to the communication module 814, which may convert the directions to a different format and send them to the vehicle systems module 818 for implementation at the vehicle. 

Further, the exemplary system 700 includes a manual input device module 820. The manual input device module 820 may receive input from a user (e.g., a startup indicator, a kill switch selection, a manual override selection, etc.), and may send such information to the controller module 812. In this way, manual user input may be provided to the exemplary system 700. 

Further still, the camera module 804, the TrailNet DNN module 806, the object detection DNN module 808, the obstacle detector module 810, the controller module, the communication module 814, and the manual input device module 820 are all implemented within a single processor 802. Communication between such modules may be made using a predetermined protocol (e.g., a ROS protocol, etc.). The vehicle systems module 818 is implemented within control hardware 816 of the vehicle that is separate from the processor 802. 

Low-Flying Autonomous MAV Trail Navigation Using Deep Neural Networks for environmental awareness 

Introduction 

In one embodiment, autonomously following a man-made trail in the forest is a challenging problem for robotic systems. Applications for such a capabilityinclude, among others, search-and-rescue, environmental mapping, wilderness monitoring, and personal videography. Micro aerial vehicles (MAVs) offer a number of advantages for solving this problem: they are not limited by the difficulty or traversability of the terrain, they are capable of high speeds, and they have the ability to quickly switch from one trail to another by flying through or over the forest. 

In order for a complete MAV system to follow a trail, it may not only detect the trail in order to determine its steering commands, but it also may be aware of its surroundings. An MAV that lacks such a capability is in danger of colliding with overhanging branches or, even worse, with people or pets using the trail. Environmental awareness is therefore one component for trail-following robots, particularly for low-flying MAVs. 

In one embodiment, an MAV system is provided for autonomous trail following. The system may use a deep neural network (DNN) (called TrailNet in this example) for determining the MAV’s view orientation and lateral offset within the trail. The computed pose may then be used for continuous control to allow the MAV to fly over forest trails. In addition, vision modules for environmental awareness may enable the MAV to detect and avoid people and pets on the trail, as well as to estimate depth in front of the robot for the purpose of reactively avoiding obstacles. All subsystems may run simultaneously in real time on board the MAV using a standalone computing device. On-board processing may be used to ensure the safety of this mission-critical system. 

In one embodiment, a hardware/software system may be implemented for environmentally aware autonomous trail navigation using DNNs that may run in real time on board an MAV. 

In another embodiment, a DNN architecture may be implemented for trail detection with improved accuracy and computational efficiency via a less confident classification scheme for more stable control as well as additional categories for estimating both view orientation and lateral offset. 

In yet another embodiment, a methodology for retraining a DNN may be implemented with 6 categories (for view orientation and lateral offset) by transfer learning from a network with 3 categories (orientation only). 

System Description

To ensure a robust and flexible platform for forest flight experiments, inexpensive off-the-shelf components may be used. One exemplary hardware setup may include a quadcopter or drone with autopilot software, an integrated computing device, and a carrier board. The vision processing may use a forward-facing camera. All processing may be done on the integrated computing device. 

The MAV may be equipped with a downward-facing, high framerate optical flow sensor with sonar and lidar. Developed the flow sensor may provide reliable metric position and attitude estimation by computing 2D optical flow on the ground, then using ground distance measurements and gyro readings to compute vehicle ground speed. Once computed, this speed may be sent to an extended Kalman filter (EKF) running on flight controller hardware to be fused with other sensor measurements (e.g., IMU) for even more precise state estimation

The diagram in Figure 9 illustrates an exemplary software architecture 900, according to one embodiment. A flight stack may be used as flight firmware 902 for the flight controller hardware autopilot 920. The flight firmware 902 may provide flexible and robust control over a range of MAV configurations. It may includesoftware-in-the-loop (SITL) simulation, which may be used for controller testing and debugging. The on-board computer may communicate with the flight firmware 902 via a predetermined protocol (e.g., MavLink, etc.). The robotic operating systemROS 904 may be run on the on-board computer. As shown in Figure 9, the architecture 900 uses the following ROS nodes 906-910: a camera driver node 906 for reading USB camera input, a joystick driver node 908 for reading game controller commands used for teleoperation (e.g., during training and for emergency override), and a messaging bridge to external autopilot module 910 for communicating with the flight firmware 902. 

In one embodiment, vision processing may be performed by three nodes 912-916. A TrailNet DNN node 912 applies a trained TrailNet DNN. An object detection node 914 runs real-time object detection DNN. An obstacle detector node 916 runs a visual odometry algorithm, whose output may be converted to a camera-centric depth map for obstacle detection and avoidance. 

The controller node 918 may be responsible for computing desired movement commands (waypoints) per current TrailNet DNN predictions, detected obstacles/objects and teleoperation commands. For safety, the teleoperation commands may take precedence over DNN predictions, so a human operator may override the MAV at any time to prevent undesirable movements. The computed waypoint may then be sent to the messaging bridge to external autopilot module 910 which resubmits it to the flight firmware 902 via a controller node 918. A righthanded ENU (east-north-up) inertial coordinate frame may be used for waypoint computation, which may be converted to the flight firmware 902‘s right-handed NED (north-east-down) coordinate frame.